DRAM integrated circuit memories are well known, and today DRAMs with capacities of 4 gigabits (4 Gb) are on the verge of being ready for production in reliable quantities. Obviously, in such integrated circuits, circuitry layout space is at a premium, as more and more devices (transistors, memory cells, etc.) are being packed into essentially-equivalent integrated circuit areas with each new DRAM generation. Such tight spacing constraints can cause, among other problems, higher coupling noise between adjacent lines on the integrated circuit.
A result of this progression is that signals are now being required to transgress long distances over the expanse of the integrated circuit. For example, in FIG. 1A, the layout of an exemplary 4 Gb DRAM 10 is shown. As it typical, the DRAM comprises bond pads 16, which normally run down the middle of the device as shown, for routing signals between the DRAM 10 and a suitable package for the DRAM (not shown). In this exemplary DRAM 10, the portion of the DRAM containing the memory cells is divided into eight banks 12, with each bank comprising four arrays 14a–14d. 
As one skilled in the art well understands, to address a particular cell in the DRAM, or group of cells together in unison (e.g., if the DRAM is greater than a ×1 device), an address needs to be input to the DRAM 10. Certain address lines (Ax) are generally designated as row address lines, while others are designated as column address lines. The address lines must be decoded so that eventually a limited subset of columns and rows in the array are activated to read/write the cells at their intersections.
Ultimately, activation of the columns and rows occurs under the control of column (bit) and row (word) line driver circuitry in the DRAM, which receive as inputs the outputs of the decoder circuitry. In the exemplary DRAM 10 of FIG. 1A, notice that the column decoders/drivers 20 are located in the middle of the device. When shown at higher magnification in FIG. 1B, it is seen that the driver circuits must drive certain signals all the way across the array 14 of cells, i.e., essentially half of the length across the expanse of the device. (Here, the term “array” is used to include the sense amplifiers and other I/O circuitry 30, such as is described in further detail in FIG. 1C, although an array can also comprise a continuous group of memory cells without such support circuitry). Specifically, column select lines 28, or CS lines or Y-select lines as they are sometimes called, are driven across the array 14 by column select driver circuits 20a, which can be viewed as part of the column decode/driver circuitry 20. As is known, the CS lines 28 are used to select a particular group of columns (bit lines) in the device, and thus can be viewed as column decoding lines.
The manner in which the CS lines 28 are used to select particular columns, or bit lines 35, in a DRAM is shown in FIG. 1C, which basically illustrates that a particular active (i.e., driven) CS line 28, can be used to enable particular I/O circuits 34 associated with the sense amps 32 at the end of the columns 35. Such selective activation of the I/O circuitry 334 by the CS lines 28 allows data to pass between the columns and the internal data path 40 of the device. In any event, it is not terribly important to an understanding of this disclosure how the CS line 28 functions to enable particular groups of columns.
What is important is recognition of a fact noted earlier: that the CS lines 28 have to transgress long distances over the integrated circuit. As one skilled in the art will appreciate, passing of signals over long signal lines is difficult. Such lines inherently have parasitic resistances and capacitances which impede the ability of the signal to propagate down the line, i.e., the signal will suffer from RC delays. As a result, the signal will travel more slowly than is ideal, and/or will be unable to achieve a desired voltage at a distance within a suitable period of time. In a worst case, and as applied to the exemplary DRAM of FIGS. 1A–1C, the CS line 28 signal will not reach the I/O circuitry 34 at various points along its length sufficiently quickly, and addressing of the cells may thus occur too slowly for proper device function.
Such RC delay problems are further exacerbated when it is considered that the CS lines 28 are logically routed through the middle of the array 14 as opposed to the peripheral areas of the integrated circuit outside of the array. Although it is known to employ various isolation schemes to try and reduce RC delays of such long-traveling signals, typical solutions are hampered by the busy nature of the signaling and the tight layout spacing in the array. Accordingly, a designer is limited in the options that can be employed to improve the signals propagation down such lines. For example, the designer cannot simply just make the lines wider in the array, or employ additional circuitry in the array (e.g., at the location of sense amp and I/O circuitry 30), as space may not be available to accommodate such modifications.
Hence, it is a goal of this disclosure to provide embodiments of a solution to the problem of degrading signal propagation along long signaling lines in integrated circuits, and specifically those passing through memory arrays.